With the explosive growth in the information created by the current society, there are ever-increasing demands for information processing, transmission, and storage. Driven by these demands, as the cornerstone of the information industry, the semiconductor industry, especially with regards to the CMOS technology, has been on a rapid growth path according to Moore's Law, thereby becoming the fastest growing industry over the past 50 years.
With the rapid development of the CMOS technology, the integration degree of devices in a semiconductor chip has been constantly increased, and the chip speed is becoming faster and faster. To meet the requirements of such integration degree and chip speed, the copper interconnect is gradually replacing the traditional aluminum interconnect for mainstream applications. At the same time, the line width of the interconnect is being reduced, wiring density is being increased, and line spacing is being decreased, which leads sharp increases in parasitic capacitance.
Device delay and interconnect delay together determine the maximum operating frequency of a circuit. As dimensions of the device continue to shrink, the interconnect delay has exceeded the device delay and become a major factor impacting the circuit operating frequency. Although using low-k dielectric can reduce the parasitic capacitance contributed by the interconnect, its application has also brought many other problems, such as integration issues and reliability issues, etc. Also, the dielectric constant of the low-k dielectric materials may reach the limit at about 1.5. Nevertheless, it is expected that the application of depositing the low-k materials by CVD processes may continue until the year of 2020. However, research and development for post-copper-interconnect technologies (including optical interconnect, carbon nano-material interconnect, cavity insulation technology, etc.) cannot be delayed.
Using the low-k materials in late-stage interconnect can greatly reduce the interconnect delay and improve chip performance. However, the conversion to the low-k (roughly defined as dielectric constant k≦3.0) material by the industry took longer than expected, because the inherent poor mechanical and chemical stability of the low-k dielectric can lead to poor assembly performance and can also pose serious reliability questions at the same time.
In order to improve the interconnect performance, copper and silicon dioxide interconnect technology was introduced as early as in 1998. However, it has been difficult to meet the requirement of reducing the dielectric constant of the late-stage insulator. Fluorine-doped silicon dioxide (k=3.7) was only introduced in the 180 nm technology, while insulating materials with k=2.7˜3.0 was not widely used even in the 90 nm technology, mostly because the reliability and yield problems were more challenging than expected when using the dual-damascene copper process to integrate these materials.
Existing advanced CMOS technology generally defines three types of interconnect: local interconnect, intermediate interconnect, and global interconnect. The local interconnect has the highest wiring density and smallest line spacing, and is often arranged at bottom levels of the interconnect structure, including contact, metal1, via1, metal2, via2 and other levels. Because the local interconnect has small size and high wiring density, the local interconnect is more susceptible to performance and reliability degrading caused by parasitic capacitance. On the other hand, the middle interconnect and global interconnect have relatively large sizes and low wiring density and, therefore, are less affected by the small-size effect.
The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.